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249 IP
101
0.118
UMC 28nm HPC Logic process PG One Port Register File with LVT
UMC 28nm HPC Logic process PG One Port Register File with LVT...
102
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UMC 28nm HPC Logic process PG-One Port Register File with HVT
UMC 28nm HPC Logic process PG-One Port Register File with HVT...
103
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UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler
UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler...
104
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UMC 28nm HPC process 2PRF with Bank2
UMC 28nm HPC process 2PRF with Bank2...
105
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UMC 28nm HPC process 2PRF with Bank2 & power gating
UMC 28nm HPC process 2PRF with Bank2 & power gating...
106
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UMC 28nm HPC process 2PRF with LVT and Bank 2
UMC 28nm HPC process 2PRF with LVT and Bank 2...
107
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UMC 28nm HPC process 2PRF, HVT & Bank2
UMC 28nm HPC process 2PRF, HVT & Bank2...
108
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UMC 28nm HPC process One Port Register File with LVT
UMC 28nm HPC process One Port Register File with LVT...
109
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UMC 28nm HPC process PG Two Port Register File
UMC 28nm HPC process PG Two Port Register File...
110
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UMC 28nm HPC process PG Two Port Register File with peri-HVT
UMC 28nm HPC process PG Two Port Register File with peri-HVT...
111
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UMC 28nm HPC process PG Two Port Register File with peri-LVT
UMC 28nm HPC process PG Two Port Register File with peri-LVT...
112
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UMC 28nm HPC process PG-2PRF with Bank4
UMC 28nm HPC process PG-2PRF with Bank4...
113
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UMC 28nm HPC process PG-2PRF with HVT Bank4
UMC 28nm HPC process PG-2PRF with HVT Bank4...
114
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UMC 28nm HPC process PG-2PRF with LVT and Bank 2
UMC 28nm HPC process PG-2PRF with LVT and Bank 2...
115
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UMC 28nm HPC process Two Port Register File
UMC 28nm HPC process Two Port Register File...
116
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UMC 28nm HPC process Two Port Register File with Bank2
UMC 28nm HPC process Two Port Register File with Bank2...
117
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UMC 28nm HPC process Two Port Register File with LVT and Bank2
UMC 28nm HPC process Two Port Register File with LVT and Bank2...
118
0.118
UMC 28nm HPC process Two Port Register File with LVT and Bank4
UMC 28nm HPC process Two Port Register File with LVT and Bank4...
119
0.118
UMC 28nm HPC process Two Port Register File with peri LVT
UMC 28nm HPC process Two Port Register File with peri LVT...
120
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UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler...
121
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UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT
UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT...
122
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UMC 28nm HPM ultra high speed register compiler
UMC 28nm HPM ultra high speed register compiler...
123
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UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler.
UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler....
124
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UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler.
UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler....
125
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UMC 40nm Low Power Process , Two Port Register File with dual power rail
UMC 40nm Low Power Process , Two Port Register File with dual power rail...
126
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UMC 40nm Low Power Process One Port Register File wit 213 cell
UMC 40nm Low Power Process One Port Register File wit 213 cell...
127
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UMC 40nm Low Power Process One Port Register File with 213 cell
UMC 40nm Low Power Process One Port Register File with 213 cell...
128
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UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral.
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral....
129
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UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral.
UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral....
130
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UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral...
131
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UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral
UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral...
132
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UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler
UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler...
133
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UMC 40nm LP Logic Process Ultra High Speed One-Port Register File_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 40nm LP Logic Process Ultra High Speed One-Port Register File...
134
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UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT
UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT...
135
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UMC 55nm eFlash peocess One Port Register File memory compiler_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 55nm eFlash peocess One Port Register File memory compiler...
136
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UMC 55nm eflash process , Two Port Register File memory compiler
UMC 55nm eflash process , Two Port Register File memory compiler...
137
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UMC 55nm EFLASH Process Two Port Register File
UMC 55nm EFLASH Process Two Port Register File...
138
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UMC 55nm EFLASH Process ULL One Port Register File
UMC 55nm EFLASH Process ULL One Port Register File...
139
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UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process...
140
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UMC 55nm Standard Performance LowK Logic Process Two-Port Register File
UMC 55nm Standard Performance LowK Logic Process Two-Port Register File...
141
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UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT...
142
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UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery...
143
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UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT...
144
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UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT...
145
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UMC 55nm ULP-SST process PG One Port Register File for periphery HVT
UMC 55nm ULP-SST process PG One Port Register File for periphery HVT...
146
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UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.
UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler....
147
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UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler
UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler...
148
0.118
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), Support retention and deep sleep modes with built-in power gating circuitry., UMC 55nm LP process
UMC 55um LP Low-K process One Port Register File compiler....
149
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One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), UMC 55nm LP process
UMC 55nm LP Logic process 0.425um2-Bit cell One Port Register File memory compiler....
150
0.118
One Port Register File Compiler IP, HJTC 0.18um pFlash process
HJTC 0.18um pFlash process synchronous Single Port Register File memory compiler....